1. Field of the Invention
The present invention relates to a multi-user interference canceller and a CDMA (Code Division Multiple Access) multi-user system in a DS-CDMA (Direct Sequence-Code Division Multiple Access) communication scheme and, more particularly, an improvement of a multi-user interference canceller characterized by the signal level of a reception signal, and a CDMA multi-user system using the same.
2. Description of the Prior Art
A multi-user interference canceller has been proposed as a method of reducing the inter- and intra-microcell interferences in a spreading spectrum multiple access (DS-CDMA), increasing the subscriber capacity, and improving speech communication quality.
Prior to demodulation of a signal from a given user k (1≦k≦K), this multi-user interference canceller generates and subtracts interference replicas of users except the user k I times (multistage) to reduce the influences of interferences from other users. The multi-user interference canceller schemes are classified into serial and parallel schemes.
The principle of the serial scheme is described in, e.g., IECE Technical Report (RCS95-50) “Sequential Channel Inference Type Serial Cancellar using a pilot symbol in DS-CDMA” or Japanese Unexamined Patent Publication No. 09-270736 (Japanese Patent No. 2737776) “DS-CDMA Multi-User Serial Interference Canceller”.
FIGS. 1 and 2 show the arrangement of an interference canceller (parallel type) described in Japanese Patent No. 2737776. This example is a 3-user canceller.
FIG. 1 is a schematic block diagram of a receiver described in this prior art and having a general DS-CDMA communication scheme. Referring to FIG. 1, an antenna 41 receives radio waves, and an RF amplifier 42 amplifies an RF signal. A variable gain amplifier 43 sets the output level of the RF signal constant. A frequency converter 44 detects a baseband signal, and an A/D converter 45 converts the baseband signal into a digital signal. An interference canceller/demodulator unit 46 cancels an interference wave from the digital signal to demodulate the original transmission data. In a negative feedback loop, a level detector 47 converts the level of the baseband signal into a DC voltage as an average or peak level of the levels accumulated for a predetermined period of time. An AGC controller 48 controls the gain of the variable gain amplifier 43 in accordance with the DC voltage to set the output level of the variable gain amplifier 43 constant.
Referring to FIG. 2, reference numeral 51 denotes a baseband reception signal demodulated by the former-stage RF demodulator and A/D-converted; 52, an ICU (Interference Canceller Unit) for generating and cancelling interference replicas; 53, an adder for adding the interference replica components of all users; 54, a delay memory for delaying and holding reception signals; 55, a subtracter for subtracting (cancelling) the interference replica components from the reception signals; 56, a line for transmitting the interference replica signal of a given user to the next stage of the given user; 57, an adder for adding the (interference) replica signal of the previous stage of the given user again (the signal components of the first stage of all users are already subtracted); and 58, a decoder for outputting a final decoded signal.
With the above arrangement, replica signals S1,1, S1,2, and S1,3 of the first to third users of the first stage are reconstructed from a reception signal r by the parallel-connected ICUs 52. The adder 53 adds these replica signals. The subtracter 55 subtracts the sum signal from the adder 53 from the original reception signal r. Before the outputs from the subtracter 55 are input to the ICUs 52 of the second stage, the signal components of the respective users are added by the adders 57. The outputs from the adders 57 are input to the ICUs 52 of the second stage, respectively. That is, an output A′i from the ith stage subtracter 55 is generally given as follows:A′i=r−Si-1,1−Si-1,2− . . . −Si-1,(k−1)−S(i-1),k−S(i-1),(k+1)− . . . −S(i-1),K  (1)As can be apparent from equation (1), the output A′i is a residual signal from which the components of all users including the component of a given user S(i-1),k are subtracted. Prior to processing for k users of the ith stage, signals S(i-1),k, i.e., the replicas of the users which are obtained in the previous stage are added by the corresponding adders 57 again and input to the corresponding ICUs 52. All these signals are chip rate signals. In the prior art of Japanese Patent No. 2737776, the memory amounts for compensating the processing delays increase in the subsequent stages. According to the above technique, however, the memory for holding reception signals can be reduced, and the apparatus can be easily implemented.
FIG. 3 is a block diagram showing the internal arrangement of the ICU 52 in the conventional scheme described in Japanese Patent No. 2737776. A multiplier 62 multiplies an input reception signal 61(r(t)) with a spread code Ck(t) of the path of the given user. Outputs from the multiplier 62 are integrated by an integrator 63 to obtain a correction detection signal. A transmission path estimator 64 obtains a transmission line fading vector ξ from the correction detection signal. A multiplier 65 multiplies a complex conjugate ξ* with the correction detection signal to correct the phase. The phase-corrected signals of the paths of the respective transmission lines are combined by a RAKE combiner 66, and a discriminator 67 decodes an original symbol sequence. To reconstruct the interference replicas, the decoded sequence is multiplied with the transmission line fading vectors of the respective path (multiplier 68) to restore the original transmission line characteristics. A multiplier 69 spreads an output from the multiplier 68 using the original spreading sequence to reconstruct the interference replica of the chip rate. An output from the multiplier 69 is transferred to the next user or stage.
In the last stage, the interference-cancelled signal is input to the decoder 58. A final decoding result is then output.
The above processing is generally digital signal processing. In processing from the input to the antenna to the input to the interference canceller, a radio reception signal input from the antenna is RF-amplified, frequency-converted, and A/D-converted. In order to convert the reception signal into a digital signal at an appropriate level, the reception signal of appropriate level must be input to the A/D converter.
For this purpose, in processing between the RF amplifier and the A/D converter, the variable gain amplifier must be arranged. In addition, an AGC (Automatic Gain Controller) must be arranged to automatically adjust the gain of the variable gain amplifier so as to monitor the input to the A/D converter and set the input level to the A/D converter almost constant.
In this interference canceller, the operation of estimating and reconstructing the interference replica from the reception signal and subtracting the interference replica from the reception signal is performed in the digital form. The operation accuracy greatly influences the characteristics of the interference canceller. To improve operation accuracy, the number of bits assigned to express the reception signal must be maximized.
Assume that digital signal processing operation for interference cancellation requires 8 bits. It is better to express the reception signal using 8 bits than to express it using a smaller number of bits because the quantization error can be reduced, and quantization accuracy can increase.
When an excessively large number of bits are assigned to the reception signal, bit overflow (the calculated value exceeds the number of bits which can be digitally expressed, and a correct value cannot be expressed) occurs in the operation process. This may degrade the interference cancellation characteristics.
In the interference canceller, not only the reception quality of a signal of interest but also the reception quality of the interference wave itself is important to perform faithful interference cancellation in accordance with its principle of operation. Assume that the difference is present between the reception wave of interest and the interference wave. In this case, when AGC control is simply performed so as to optimize only the reception characteristics of the reception characteristics of the wave of interest, the level of the interference wave becomes excessively low, the number of bits assigned to the reception wave of interest decreases, and a sufficient operational accuracy cannot be assured. This degrades the accuracy of the reconstructed interference replica. As a result, the reception characteristics upon interference cancellation cannot be improved.
The input to the A/D converter must be controlled so as to determine bit assignment for minimizing the degradation of the total characteristics by the operation errors in the above processing.
In the prior art described above, the signal level prior to A/D conversion is simply detected, and AGC control prior to A/D conversion is performed in accordance with the magnitude of the detected level. The following control methods for the above operation are available: a method of keeping the average level constant; a method of suppressing the peak level to a predetermined level; and a method of inhibiting a change in gain with an AGC control hysteresis until a change in level to some extent occurs. Either method controls the level prior to A/D conversion. Therefore, optimal reception characteristics are not always obtained under various conditions described above.